Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537353
Ming-Jui Li, M. Breeden, V. Wang, Nyi Myat Khine Linn, C. Winter, A. Kummel, M. Bakir
A Cu-Cu bonding approach using low temperature (200 °C) selective Co ALD is demonstrated for Cu pads that are separated by 200 nm. The bonding testbed is characterized before and after Co ALD by SEM and EDS to confirm the feasibility of the approach. AFM and XPS are used to measure the selectivity of Co ALD on Cu and SiO2 surfaces.
{"title":"Characterization of Low-Temperature Selective Cobalt Atomic Layer Deposition (ALD) for Chip Bonding","authors":"Ming-Jui Li, M. Breeden, V. Wang, Nyi Myat Khine Linn, C. Winter, A. Kummel, M. Bakir","doi":"10.1109/IITC51362.2021.9537353","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537353","url":null,"abstract":"A Cu-Cu bonding approach using low temperature (200 °C) selective Co ALD is demonstrated for Cu pads that are separated by 200 nm. The bonding testbed is characterized before and after Co ALD by SEM and EDS to confirm the feasibility of the approach. AFM and XPS are used to measure the selectivity of Co ALD on Cu and SiO2 surfaces.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74381977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537485
M. Hosseini, G. Martinez, M. H. van der Veen, N. Jourdan, E. Litta, N. Horiguchi
The focus of this paper is on automatic methodology to detect the sidewall voids in narrow trenches filled by Ru. For this purpose, we applied image processing techniques for image recognition and labeling of images obtained by high-angle-annular-dark-field scanning TEM (HAADF-STEM). Roughly 3300 STEM images of narrow trenches with BCD of 10nm and AR>8 were labeled. This paper demonstrates the versatility and potential of image processing to address the automated void detection in advance MOL applications.
{"title":"Automated voids detection for metal filled trenches with bottom CD of 10nm","authors":"M. Hosseini, G. Martinez, M. H. van der Veen, N. Jourdan, E. Litta, N. Horiguchi","doi":"10.1109/IITC51362.2021.9537485","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537485","url":null,"abstract":"The focus of this paper is on automatic methodology to detect the sidewall voids in narrow trenches filled by Ru. For this purpose, we applied image processing techniques for image recognition and labeling of images obtained by high-angle-annular-dark-field scanning TEM (HAADF-STEM). Roughly 3300 STEM images of narrow trenches with BCD of 10nm and AR>8 were labeled. This paper demonstrates the versatility and potential of image processing to address the automated void detection in advance MOL applications.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"580 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77367062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537396
D. Sil, Y. Sulehria, O. Gluschenkov, T. Nogami, R. Cornell, A. Simon, J. Li, J. Demarest, B. Haran, C. Lavoie, J. Jordan-Sweet, V. Stanic, J. Liu, K. Huet, F. Mazzamuto
A novel nanosecond (ns) laser anneal (multiple laser shots at sub-melting low laser energy) was employed to reduce the blanket sheet resistance of Ru thin films deposited by physical vapor deposition (PVD). The laser anneal was conducted after PVD Ru deposition and then followed up with a standard 400°C anneal in a forming gas environment. Blanket sheet R decreased by 30% for the laser + furnace annealed Ru films, whereas the drop for just 400°C furnace annealed Ru films was only 18%. Multiple laser exposures at an optimized laser fluence was identified as a key factor in enabling this benefit at BEOL compatible thermal budget suitable for scaled-down Ru interconnects.
{"title":"Impact of Nanosecond Laser Anneal on PVD Ru Films","authors":"D. Sil, Y. Sulehria, O. Gluschenkov, T. Nogami, R. Cornell, A. Simon, J. Li, J. Demarest, B. Haran, C. Lavoie, J. Jordan-Sweet, V. Stanic, J. Liu, K. Huet, F. Mazzamuto","doi":"10.1109/IITC51362.2021.9537396","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537396","url":null,"abstract":"A novel nanosecond (ns) laser anneal (multiple laser shots at sub-melting low laser energy) was employed to reduce the blanket sheet resistance of Ru thin films deposited by physical vapor deposition (PVD). The laser anneal was conducted after PVD Ru deposition and then followed up with a standard 400°C anneal in a forming gas environment. Blanket sheet R decreased by 30% for the laser + furnace annealed Ru films, whereas the drop for just 400°C furnace annealed Ru films was only 18%. Multiple laser exposures at an optimized laser fluence was identified as a key factor in enabling this benefit at BEOL compatible thermal budget suitable for scaled-down Ru interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"61 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86241646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537501
F. Cerio, Rutvik J. Mehta, P. Turner, Jinho Kim, R. Caldwell
As feature sizes shrink with each integration node, wire and interconnect resistivity in the back end of the line increasingly becomes a challenge due to size dependent effects. Microstructural control of metal thin films is critical for accessing the lowest resistivities alongside materials choice. In this paper, we describe depositing a metal material onto a substrate via ion beam deposition with assist in a process chamber at a temperature of at least 250°C to produce ultra-low resistivity metal films. Ion beam deposited thin tungsten films were grown with large and highly oriented α(110) grains having a resistivity less than 9 μΩ-cm and thickness less than 300 Å, with no discernable β-phase, presaging benefits for memory and logic applications using tungsten for wiring.
{"title":"Microstructural Optimization of Tungsten for Low Resistivity Using Ion Beam Deposition","authors":"F. Cerio, Rutvik J. Mehta, P. Turner, Jinho Kim, R. Caldwell","doi":"10.1109/IITC51362.2021.9537501","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537501","url":null,"abstract":"As feature sizes shrink with each integration node, wire and interconnect resistivity in the back end of the line increasingly becomes a challenge due to size dependent effects. Microstructural control of metal thin films is critical for accessing the lowest resistivities alongside materials choice. In this paper, we describe depositing a metal material onto a substrate via ion beam deposition with assist in a process chamber at a temperature of at least 250°C to produce ultra-low resistivity metal films. Ion beam deposited thin tungsten films were grown with large and highly oriented α(110) grains having a resistivity less than 9 μΩ-cm and thickness less than 300 Å, with no discernable β-phase, presaging benefits for memory and logic applications using tungsten for wiring.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"768 ","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91444979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537519
K. S. Yew, Yi Jiang, W. Yi, R. Chockalingam, R. X. Ong, Bo Li, Juan Boon Tan
Limiting the minimum spacing design rule of intra-metal lines and skipping the inter-metal layer in interconnects for more oxide spacing in order to improve TDDB margin for HV applications is not viable as it severely compromises the competitiveness of chip design. We demonstrated that with stringent control of the variation in oxide spacing between inter-metal layers, it is possible to improve TDDB margin for HV applications up to 12V for the specific low-k interconnects integration process. This technique provides a solution for cost saving without compromising reliability aspect.
{"title":"Interconnects Variability Control for High Voltage Applications","authors":"K. S. Yew, Yi Jiang, W. Yi, R. Chockalingam, R. X. Ong, Bo Li, Juan Boon Tan","doi":"10.1109/IITC51362.2021.9537519","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537519","url":null,"abstract":"Limiting the minimum spacing design rule of intra-metal lines and skipping the inter-metal layer in interconnects for more oxide spacing in order to improve TDDB margin for HV applications is not viable as it severely compromises the competitiveness of chip design. We demonstrated that with stringent control of the variation in oxide spacing between inter-metal layers, it is possible to improve TDDB margin for HV applications up to 12V for the specific low-k interconnects integration process. This technique provides a solution for cost saving without compromising reliability aspect.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"102 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79514081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537541
G. Sisto, B. Chehab, B. Genneret, R. Baert, R. Chen, P. Weckx, J. Ryckaert, R. Chou, G. van der Plas, E. Beyne, D. Milojevic
We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the backside to frontside connectivity are included: μTSVs and nTSVs (respectively 0.5μm, 0.09μm diameter and 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads are used to deliver power to the second die in the stack. A commercial power analysis tool is extended to support both the TSV and the pads structures, to tackle both inter-die and on-die power delivery challenges. A L1 cache memory implemented on the top of a core is used as test case to assess the performance of the proposed metal stack. A 69% reduction in average static IR-drop is observed with the BS-PDN compared to the conventional frontside. Further, 81% and 77% average and peak IR-drop reductions are obtained with nTSV compared to μTSV.
{"title":"IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs","authors":"G. Sisto, B. Chehab, B. Genneret, R. Baert, R. Chen, P. Weckx, J. Ryckaert, R. Chou, G. van der Plas, E. Beyne, D. Milojevic","doi":"10.1109/IITC51362.2021.9537541","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537541","url":null,"abstract":"We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the backside to frontside connectivity are included: μTSVs and nTSVs (respectively 0.5μm, 0.09μm diameter and 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads are used to deliver power to the second die in the stack. A commercial power analysis tool is extended to support both the TSV and the pads structures, to tackle both inter-die and on-die power delivery challenges. A L1 cache memory implemented on the top of a core is used as test case to assess the performance of the proposed metal stack. A 69% reduction in average static IR-drop is observed with the BS-PDN compared to the conventional frontside. Further, 81% and 77% average and peak IR-drop reductions are obtained with nTSV compared to μTSV.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"17 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78397441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537553
Xiaodong Li, R. Chockalingam, P. Ang, W. Neo, Juan Boon Tan
Galvanic corrosion of copper bondpad is studied with various copper barrier liner compositions in a unbiased highly accelerated stress test (uhast) condition. It is observed that the delamination at the bimetallic interface between the barrier liner and bulk copper has a strong dependence of N/Ta ratio of the liner. The delamination mechanism is explained and attributed to the galvanic corrosion, due to the presence of electrochemical potential difference between the barrier liner and bulk copper, which is shown to be significantly suppressed by increasing the nitrogen content composition of the liner.
{"title":"A study on the nitridation of barrier liner contribution to galvanic corrosion of copper bondpad","authors":"Xiaodong Li, R. Chockalingam, P. Ang, W. Neo, Juan Boon Tan","doi":"10.1109/IITC51362.2021.9537553","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537553","url":null,"abstract":"Galvanic corrosion of copper bondpad is studied with various copper barrier liner compositions in a unbiased highly accelerated stress test (uhast) condition. It is observed that the delamination at the bimetallic interface between the barrier liner and bulk copper has a strong dependence of N/Ta ratio of the liner. The delamination mechanism is explained and attributed to the galvanic corrosion, due to the presence of electrochemical potential difference between the barrier liner and bulk copper, which is shown to be significantly suppressed by increasing the nitrogen content composition of the liner.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85336514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537559
S. You, He Ren, M. Naik, Lu Chen, Feng Chen, C. L. Cervantes, Xiangjing Xie, K. Kashefizadeh
The continued scaling in logic technology poses significant challenges such as huge resistance-capacitance (RC) delays due to the shrinkage in dimensions. To address the BEOL Cu interconnect portion of RC delays, reducing the via resistance through Tantalum Nitride (TaN) barrier layer adjustment is critical while in the meantime must meet the reliability requirement. TaN barrier on via bottom contribute the major portion of Via R due to its high resistivity. Thinner TaN barrier approach, however, is limited due to its degraded barrier performance; In this paper, we presented the study of selective barrier approach that utilize gas phase metal passivation method to provide barrier free via bottom. >50% via R reduction is demonstrated with no reliability degradation.
{"title":"Selective Barrier for Cu Interconnect Extension in 3nm Node and Beyond","authors":"S. You, He Ren, M. Naik, Lu Chen, Feng Chen, C. L. Cervantes, Xiangjing Xie, K. Kashefizadeh","doi":"10.1109/IITC51362.2021.9537559","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537559","url":null,"abstract":"The continued scaling in logic technology poses significant challenges such as huge resistance-capacitance (RC) delays due to the shrinkage in dimensions. To address the BEOL Cu interconnect portion of RC delays, reducing the via resistance through Tantalum Nitride (TaN) barrier layer adjustment is critical while in the meantime must meet the reliability requirement. TaN barrier on via bottom contribute the major portion of Via R due to its high resistivity. Thinner TaN barrier approach, however, is limited due to its degraded barrier performance; In this paper, we presented the study of selective barrier approach that utilize gas phase metal passivation method to provide barrier free via bottom. >50% via R reduction is demonstrated with no reliability degradation.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82073973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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