Wallace-tree based timing-driven synthesis of arithmetic circuits

Abstract

Wallace-tree style implementations have been proven to be effective schemes for fast computations of arithmetic. This paper generalizes the concept of Wallace's scheme to include 'uneven' arrival times of input operands of the arithmetic circuit. More specifically, for an arithmetic expression in the circuit, we proposed a synthesis algorithm for solving the problem of transforming the expression into a form of the Wallace-tree structure that leads to a minimal timing of the circuit. This practically enables an extensive utilization of Wallace's scheme over the arithmetic circuit, thereby reducing the timing of circuit more effectively. Experimental results are provided to show the effectiveness of the proposed algorithm, over the conventional two-step (RTL and logic) optimization.