C. Matsui, S. Fukuyama, Atsuna Hayakawa, K. Takeuchi
{"title":"Application-Induced Cell Reliability Variability-Aware Approximate Computing in TaOx-based ReRAM Data Center Storage for Machine Learning","authors":"C. Matsui, S. Fukuyama, Atsuna Hayakawa, K. Takeuchi","doi":"10.23919/VLSIT.2019.8776565","DOIUrl":null,"url":null,"abstract":"This paper proposes Variability-Aware Approximate Computing (V-AC) for TaOx ReRAM storage at data centers. For the first time, this paper shows that application-induced variability degrades the performance. To solve this problem, V-AC utilizes error resilience of machine learning (ML) application and reduces bit-error rate (BER) of typical cells by removing extra data copy and enlarging BER difference among cells. By combining device measurement and system emulations, this paper realizes system, circuit and device codesign (SCDCD). V-AC is key enabling technology to push the limits of performance, power, chip size and scaling of ReRAM for ML. Performance, energy and cell area of ReRAM storage improves by 7.0 times, 90% and 8.5%, respectively.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"29 1","pages":"T234-T235"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper proposes Variability-Aware Approximate Computing (V-AC) for TaOx ReRAM storage at data centers. For the first time, this paper shows that application-induced variability degrades the performance. To solve this problem, V-AC utilizes error resilience of machine learning (ML) application and reduces bit-error rate (BER) of typical cells by removing extra data copy and enlarging BER difference among cells. By combining device measurement and system emulations, this paper realizes system, circuit and device codesign (SCDCD). V-AC is key enabling technology to push the limits of performance, power, chip size and scaling of ReRAM for ML. Performance, energy and cell area of ReRAM storage improves by 7.0 times, 90% and 8.5%, respectively.