A novel double slope analog-to-digital converter for a high-quality 640/spl times/480 CMOS imaging system

Abstract

In this paper, a novel double slope ADC (Analog-to-Digital Converter) for imaging applications is proposed. With this conversion technique, the resolution of images can be increased especially for low illumination environments while maintaining wide dynamic range. The proposed double slope ADC is implemented with a parallel bank of 640 pseudo-l0b ADCs in a 3.3 V single chip digital CMOS image sensor with 640/spl times/480 (VGA) pixel array, 3.04 kB DRAM line buffer, and digital control block using a 0.5 /spl mu/m single poly, triple metal DRAM baseline.