Code generation for embedded processors with complex instructions

Abstract

Code generation for embedded processors often encounters the problem of using complex instructions. The problems come from the heterogeneous register architecture of the embedded processors, small number of registers, and instructions with complex behaviors. In this paper we propose some techniques for using complex instructions. One of them is a simple technique to use MAC instruction (Modified Pattern Matching). The other two techniques are implemented in the Postpass Optimizer that optimizes the generated code with hardware loop instructions and post-increment or post-decrement addressing modes. Experimental results are also presented.