A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

Abstract

A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.