Y.H. Kim, J. Nam, Y. Sohn, S. Heo, S. Lee, H.J. Park, Y. han, J. Doh, Y.J. Choi, J. Choi, J. Choi, C. Park
{"title":"Two-phase boosted voltage generator [CMOS DRAMs]","authors":"Y.H. Kim, J. Nam, Y. Sohn, S. Heo, S. Lee, H.J. Park, Y. han, J. Doh, Y.J. Choi, J. Choi, J. Choi, C. Park","doi":"10.1109/ICVC.1999.821007","DOIUrl":null,"url":null,"abstract":"A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and V/sub TN/ respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 V/sub TN/ respectively. Also the pumping current was increased in the new circuit.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"62 1","pages":"586-589"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.821007","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and V/sub TN/ respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 V/sub TN/ respectively. Also the pumping current was increased in the new circuit.