Enhancing uniformity of borderless via resistance by HDP oxide technology

Abstract

This paper describes part of the technology of a five level metal interconnection method for a 25C07 (gate CD: 0.25 /spl mu/m, metal1 pitch design rule: 0.76 /spl mu/m) CMOS device. In order to achieve the stable interconnection of metal lines, first we should open the via holes very clearly and uniformly through a via patterning/etching process, and not only the strong barrier metal (Ti/TiN) property for surrounding the via hole, especially the bottom corner, but also the proper W filling in the via hole, is required. Another important factor is the Intermetal Dielectric Material (IMD). When we have no room (almost zero) of the via hole to endlap the bottom metal, the IMD material can give effect to the via resistance. The objective of this experiment is to look at the via resistance difference in the zig-zag test pattern (via CD: 0.33 /spl mu/m, via endlap to bottom metal: 0.1 /spl mu/m, via sidelap to bottom metal: 0.02 /spl mu/m, metal width/space: 0.4 /spl mu/m/0.36 /spl mu/m) due to the IMD materials (HDP USG vs. SOG) and, finally, compare the device yield. High Density Plasma CVD (HDP USG) and SOG (Spin On Glass) were performed as a split corner of IMD layer deposition. Every process step, from pad oxidation to passivation, except IMD layer deposition( HDP CVD and. SOG coating and cure), was done simultaneously under the completely same condition. In this work, we monitored the "process in line data" such as global planarization of post IMD CMP and via photo CD/etch CD to correlate the electrical via resistance data with "process in line data".