Yield/reliability enhancement using automated minor layout modifications

Abstract

This paper reports a new layout modification tool for the automation of yield and reliability enhancement of IC layout. The peye tool combines the eye (Edinburgh Yield Estimator) with Perl (Practical Extraction and Reporting Language). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The new peye tool has been interfaced with a sampling based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. Results of layout modifications are presented.