Interconnects Variability Control for High Voltage Applications

Abstract

Limiting the minimum spacing design rule of intra-metal lines and skipping the inter-metal layer in interconnects for more oxide spacing in order to improve TDDB margin for HV applications is not viable as it severely compromises the competitiveness of chip design. We demonstrated that with stringent control of the variation in oxide spacing between inter-metal layers, it is possible to improve TDDB margin for HV applications up to 12V for the specific low-k interconnects integration process. This technique provides a solution for cost saving without compromising reliability aspect.