Realistic Solder Joint Geometry Integration with Finite Element Analysis for Reliability Evaluation of Printed Circuit Board Assembly

Abstract

Solder joint failure is a serious reliability concern in area array technologies, such as flip chip (FC), Plastic Ball Grid Array (PBGA), Fan-In and Fan-Out Wafer Level Packages (WLP) of advanced IC package. The selection of different substrate materials, solder material, molding compound, stacked dies structure, and laminate material could affect the solder joint stress-strain condition. It is therefore important to know the solder joint shape and standoff height accurately after the reflow process to estimate the reliability of solder joint assembly in three aspects: temperature cycling, mechanical shock, and vibration. A strategy for importing three-dimensional computed tomography (CT) data into a Finite Element based reliability evaluation is outlined. Three dimensional CT is a very fast, non-destructive automatic inspection machine. Moreover, with new version of CT scanning in high resolution, full solder geometry is reconstructed throughout the entire area array on printed circuit board assembly (PCBA). Finite Element Analysis (FEA) is used to calculate the accumulated plastic work per cycle for BGA packages on PCBA. The accumulated plastic work is then used to calculate the number of cycles to failure based on thermal fatigue life model of solder joints. FEA is also used to predict the damage index during shock and vibration event, and used to study mounting configurations and structural integrity of solder joints. The reliability results showed a good agreement with the experimental results based on two designs on new solid state drive (SSD) form factor. It was found that the cycles to failure and critical location among four corner joints match well with experimental results. From simulation results, it was also found that new design was much improved over old design. The methodology was extended to reliability evaluation for BGA packages such as FC controller, DDR SDRAM, and NAND packages on PCBA. Results demonstrate the excellent capability of the proposed integration tools for predicting the robustness of PCBA. The proposed approach greatly reduces reliability evaluation time, shortens the product life cycle development, and is more cost effective to address the reliability issues.