A folded bit-line architecture for high speed CMOS SRAM

Abstract

This paper describes a new architecture and schemes for a high speed SRAM. It is summarized as follows:1) a Folded Bit-Line Architecture (FBLA) to reduce the delay time of bit-line by decreasing the parastic capacitance, to reduce the area. 2) a Double Word-Line Activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and 3) a high speed sensing scheme to decrease the delay time of the sense amplifier. To verify the above, a 8 kb SRAM was designed using 0.6 /spl mu/m CMOS technology. It realized a 600 Mbyte/s(300 M/spl times/8/spl times/2) data-rate and the die size is 2.8 mm/spl times/0.85 mm.