Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash

H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash","authors":"H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.23919/VLSIT.2019.8776483","DOIUrl":null,"url":null,"abstract":"The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"31 1","pages":"T210-T211"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
超薄体(Tsi~3nm)器件的优势提升3D NAND闪存的存储窗口
采用极薄体(ETB, Tsi=3nm)器件的优势已在3D NAND闪存测试芯片中得到验证。对于使用ETB多晶硅的器件,观察到净P/E存储器窗口增益为>1.3V。这种可观的增益可以用“量子约束”来解释,它提高了有效的Si带隙,从而降低了隧道势垒的高度。仿真结果表明,当Tsi=3nm时,电子和空穴的等效势垒高度分别降低了~0.16eV和0.07eV。同时,极薄的多晶硅通道可以将S.S.提高到接近250mV/dec,接近体块2D Flash器件。然而,当Tsi=3nm时,由于更大的有效质量或更高的接触电阻,Idsat仅退化到160nA。降低的Idsat可以通过较低的Isense<30nA进行页面缓冲电路调优。超薄的机身显著降低了随机电报噪声(RTN),并且在MLC/TLC操作中显示出更紧密的程序验证(PV)分布。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Economics of semiconductor scaling - a cost analysis for advanced technology node Transient Negative Capacitance as Cause of Reverse Drain-induced Barrier Lowering and Negative Differential Resistance in Ferroelectric FETs Confined PCM-based Analog Synaptic Devices offering Low Resistance-drift and 1000 Programmable States for Deep Learning High Performance Heterogeneous Integration on Fan-out RDL Interposer Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1