W. Chien, H. Ho, C. Yeh, C.H. Yang, H. Cheng, W. Kim, I. Kuo, L. Gignac, E. Lai, N. Gong, Y. Chou, C. Cheng, Y. Lin, J. Papalia, F. Carta, A. Rav, R. Bruce, M. Briahtxky, H. Lung
{"title":"Comprehensive Scaling Study on 3D Cross-Point PCM toward 1Znm Node for SCM Applications","authors":"W. Chien, H. Ho, C. Yeh, C.H. Yang, H. Cheng, W. Kim, I. Kuo, L. Gignac, E. Lai, N. Gong, Y. Chou, C. Cheng, Y. Lin, J. Papalia, F. Carta, A. Rav, R. Bruce, M. Briahtxky, H. Lung","doi":"10.23919/VLSIT.2019.8776516","DOIUrl":null,"url":null,"abstract":"We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"30 1","pages":"T60-T61"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776516","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.
我们提出了一种用于存储类存储器(SCM)应用的lZnm节点三维交叉点PCM (XPCM)的缩放研究。低工作电流和低金属线负载电阻是为了避免在交叉点阵列中的宽工作电压分布。首次研究了1S1R OTS-PCM的交流阈值电压(Vth)对运行方案的影响。为了达到每芯片Tera位密度，需要6层具有高电压和低漏电流的具有OTS的1Znm 3D XPCM，以及可扩展的外围电路。
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
