Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology

Abstract

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].