A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation

Abstract

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $\text{D}_{\text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $\text{Gm}_{\text{SAT}}/\text{SS}_{\text{SAT}}$ of 5.4 at 73 nm Lg.