{"title":"High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme","authors":"Chang-Ki Kwon, KwangMyoung Rho, Kwyro Lee","doi":"10.1109/ICVC.1999.820940","DOIUrl":null,"url":null,"abstract":"In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The simulation results show that the reduction of approximately 20% speed and 40% energy consumption is achieved for the proposed circuits, as compared with the conventional full CMOS inverters at low supply voltage (=1.5 V).","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820940","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The simulation results show that the reduction of approximately 20% speed and 40% energy consumption is achieved for the proposed circuits, as compared with the conventional full CMOS inverters at low supply voltage (=1.5 V).