Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node

Abstract

Due to the slowdown in gate pitch scaling linked to fundamental physical limitations, standard cell (SDC) height reduction becomes a key to achieve the scaling targets. In this work, a two-level (2L) middle of line (MOL) scheme based on a forksheet (FSH) device architecture and Vertical-Horizontal-Vertical (VHV) routing style is proposed to achieve 4-Track (4T) SDC template. The proposed architecture achieves 21% higher Power-Performance-Area (PPA) compared to the traditional 5T-HVH FSH architecture with limited additional process complexity and Cost (C).