Optimization of oxide spacer etch process for 0.35 um CMOS transistor

Abstract

Higher yield may be achieving through tighter control over transistor speed. At National, speed is measured by testing the critical parameter: saturation current (Idsat). A key variable controlling Idsat turned out to be the spacer etch. Across wafer etch uniformity was substantial enough to span over 60% of the Idsat spec range. This left little room for wafer-to-wafer or lot-to-lot variation. To improve the spacer etch, gas flows and power setting were optimizes through a series of designed experiments. Ultimately, across wafer spacer etch uniformity improved approximately 50%, which improved across wafer Idsat uniformity by approximately 33%.