Advanced interconnect technologies for ULSI scaling

Abstract

This paper describes advanced interconnect technologies with respect to ULSI scaling. Copper interconnects and low-k interlayer dielectrics, in conjunction with chemical mechanical polishing (CMP) planarization, are key technologies for future scaled ULSIs to reduce the RC delay of global interconnects. Salicide is an essential technology for sub-quarter micron CMOS gate and source/drain electrodes to reduce the parasitic resistances of transistors for high-speed logic ULSIs. Consequently, both resistivity and capacitance are key factors for materials used in the interconnect technologies for ULSI scaling.