12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

Abstract

For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205\ \mu \text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.