DRAM technology: outlook and challenges

Abstract

As we approach the new millenium DRAM technology is faced with a number of significant new challenges in addition to those associated with the historical DRAM scaling paradigm. Continued lithographic capability scaling is of course required, but this must now be accomplished on an accelerated schedule at a time when the overall development infrastructure (masks, inspection, repair, steppers, resists) is struggling to keep up with historical trends. Similar limitations exist for continued scaling of many cell technologies: node dielectric thickness, array transistor threshold/leakage control, support transistor performance, high aspect ratio metallization and gap fill all face fundamental materials or physics limitations which require significant effort and cost to overcome. At the same time. Continued scaling in support of the historical 27%/bit/yr cost decline requires breakthroughs in both cell technology and product architecture to address the theoretical cell area limit of 8 lithographic squares for the classical folded bitline architecture. Finally, these challenges are appearing at a time when the DRAM marketplace is diverging into multiple high performance interface requirements which stress these technology features even further while market pricing continues to put extreme pressure on process and development cost containment. The author reviews many of these challenges, comments on the details of the technical issues and then outlines some alternatives which may address the concerns.