Reduce scrap: control oxide loss in SC1

Heather Maines, M. Rathmell, L. Veldhuis
{"title":"Reduce scrap: control oxide loss in SC1","authors":"Heather Maines, M. Rathmell, L. Veldhuis","doi":"10.1109/ASMC.2002.1001600","DOIUrl":null,"url":null,"abstract":"In this study, we characterize thermal silicon dioxide, plasma enhanced CVD tetraorthosilicate oxide (PECVD TEOS) and phosphorous doped silicate glass (PSG) etch rates in SC1 as a function of temperature and concentration. We also measure the effect of implant screen oxide loss in SC1 on transistor voltage turn on and elucidate ways to reduce scrap due to oxide loss in SC1.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"半导体技术","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ASMC.2002.1001600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In this study, we characterize thermal silicon dioxide, plasma enhanced CVD tetraorthosilicate oxide (PECVD TEOS) and phosphorous doped silicate glass (PSG) etch rates in SC1 as a function of temperature and concentration. We also measure the effect of implant screen oxide loss in SC1 on transistor voltage turn on and elucidate ways to reduce scrap due to oxide loss in SC1.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
减少废料:控制SC1中的氧化物损失
在这项研究中,我们表征了SC1中热二氧化硅、等离子体增强CVD四正硅酸盐(PECVD TEOS)和掺磷硅酸盐玻璃(PSG)蚀刻速率与温度和浓度的关系。我们还测量了SC1中植入屏氧化物损耗对晶体管电压导通的影响,并阐明了减少SC1中氧化物损耗造成的废料的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
8436
期刊最新文献
A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies Ultra-dilute silicon wafer clean chemistry for fabrication of RF microwave devices Planarization yield limiters for wafer-scale 3D ICs Statistical modeling and analysis of wafer test fail counts An approach for improving yield with intentional defects
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1