Analysis of edge placement error (EPE) at the 5nm node and beyond

R. Socha
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Abstract

The resolution concept of k1 is introduced along with various methods to reduce the k1 through resolution enhancement techniques. The edge placement error (EPE) of a 5nm node SRAM is analyzed in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization (SMO), and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matching error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Since SEPE is difficult to reduce, more emphasis needs to be placed on reducing the overlay EPE in order to reduce the total EPE.
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5nm及以上节点边缘放置误差(EPE)分析
介绍了k1的分辨率概念,以及通过分辨率增强技术降低k1的各种方法。详细分析了5nm节点SRAM在通孔0 (V0)层与金属0 (M0)层对齐时的边缘放置误差(EPE)。这些层通过源掩模优化(SMO)进行优化,并从随机因素、全局临界尺寸均匀性(CDU)、覆盖、光学接近校正(OPC)误差和扫描仪匹配误差中最小化EPE。EPE的最大误差来源是随机EPE (SEPE),其中产生的最大EPE为5nm。由于EPE难以降低,因此需要更加重视降低覆盖EPE,以降低总EPE。
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