A novel charge pump PLL with reduced jitter characteristics

Abstract

A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.