Critical path analysis considering the signal transition time

Abstract

This paper proposes a critical path analysis algorithm that considers the effects of the signal transition time. First, the proposed algorithm finds the possible minimum transition time and the possible maximum transition time. Then, within the range, it extracts the maximum delay of each gate and computes the PERT delay. Finally, it performs depth first search under searching condition that the sum of a current searching path and a PERT delay is larger than that of critical path evaluated already. Experimental results show that the proposed algorithm finds the correct critical paths of the ISCAS 85 benchmark circuits where the existing critical path analysis methods fail. Experimental results also show that the complexity of the proposed algorithm is linear with the circuit size.