Advanced interconnect challenges beyond 5nm and possible solutions

Abstract

As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as a new liner that can enable more aggressive thickness scaling. To improve capacitance, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss is mainly attributed to micro bridge, also known as stochastic printing failures of EUV lithography, or scaling induced Cu void or bridge defects. New photoresists or etch process recipes are being explored in order to address the micro bridge. Cu-fill friendly damascene profile is being introduced to suppress Cu void defects. Since rising BEOL cost is a critical challenge, single EUV patterning to replace double patterning is being actively investigated. In parallel to the conventional scaling, disruptive interconnect architectural changes such as backside power distribution network, and innovative materials such as alternative conductors, and 2D barriers / liners need to be considered.