Interleaving partial bus-invert coding for low power reconfiguration of FPGAs

Abstract

The authors propose a bus encoding scheme which partitions the configuration data sequence of an FPGA into sub-sequences and applies partial bus-invert coding to each sub-sequence to reduce the number of data bus transitions in reconfiguring the FPGA. Experimental results show that the proposed method gives 12.79%/spl sim/17.06% more reduction of bus transitions on average compared with the conventional bus-invert coding, partial bus-invert coding, and the Beach coding.