Contact module progress and challenges in advanced CMOS technologies

Abstract

In this invited paper, we demonstrate that the contact interface resistance is a major bottleneck for advanced FinFET performance scaling (38% of the external resistance at 45nm gate pitch). After analyzing the key components defining the contact interface resistivity (active doping level, Schottky barrier height, contact area), we review the engineering techniques available to improve this critical bottleneck. We propose that the contact area engineering is an essential engineering direction to unlock the benefits of advanced CMOS technology performance and discuss some related processing techniques such as the superconformal Ti deposition.