Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

Abstract

In this paper the dependence of interconnect line-induced delay time on the repeater size is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as repeater size increases. However there exists a point where the delay time becomes minimum when both of resistance and capacitance of interconnect line becomes larger than those of transistor. The optimum repeater size is obtained using an analytic equation and the experimental results showed good agreement with the calculation.