A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

Abstract

This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.