垂直通管设计，用于sub- 100nm DRAM技术

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015443

K. McStay, D. Chidambarrao, J. Mandelman, J. Beintner, H. Tews, M. Weybright, G. Wang, Y. Li, K. Hummler, R. Divakaruni, W. Bergner, E. Crabbé, G. Bronner, W. Müller

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引用次数: 3

摘要

8F/sup 2/垂直晶体管DRAM单元是一种成本效益高、对岩石友好的结构，适合缩放到100纳米以下的基本规则。在本文中，我们报告了用于超密集DRAM技术的垂直通道晶体管的器件设计考虑。一种满足1fA断流要求的双栅垂直DRAM通流晶体管，其电流驱动是同类175 nm平面器件的两倍。此外，强调了垂直设备的独特结构特征。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Vertical pass transistor design for sub-100 nm DRAM technologies

The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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