T. Sugizaki, M. Nakamura, M. Yanagita, M. Honda, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, I. Yamamura, K. Yagami, T. Oda
{"title":"具有选择性外延阳极(SEA)的超高速体晶闸管sram (BT-RAM)电池","authors":"T. Sugizaki, M. Nakamura, M. Yanagita, M. Honda, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, I. Yamamura, K. Yagami, T. Oda","doi":"10.1109/IEDM.2006.346984","DOIUrl":null,"url":null,"abstract":"We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ultra High-speed Novel Bulk Thyristor-SRAM (BT-RAM) Cell with Selective Epitaxy Anode (SEA)\",\"authors\":\"T. Sugizaki, M. Nakamura, M. Yanagita, M. Honda, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, I. Yamamura, K. Yagami, T. Oda\",\"doi\":\"10.1109/IEDM.2006.346984\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond\",\"PeriodicalId\":366359,\"journal\":{\"name\":\"2006 International Electron Devices Meeting\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2006.346984\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond
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