电化学抛光易碎多孔低k/铜集成

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015376

S. Takahashi, K. Tai, H. Ohtorii, N. Komai, Y. Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M. Ishihara, T. Nogami

{"title":"电化学抛光易碎多孔低k/铜集成","authors":"S. Takahashi, K. Tai, H. Ohtorii, N. Komai, Y. Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M. Ishihara, T. Nogami","doi":"10.1109/VLSIT.2002.1015376","DOIUrl":null,"url":null,"abstract":"A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Fragile porous low-k/copper integration by using electro-chemical polishing\",\"authors\":\"S. Takahashi, K. Tai, H. Ohtorii, N. Komai, Y. Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M. Ishihara, T. Nogami\",\"doi\":\"10.1109/VLSIT.2002.1015376\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015376\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015376","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

通过应用我们先前报道的[1]电化学抛光(ECP)技术，我们成功地将一种脆弱的多孔超低钾(k=2.2)二氧化硅集成到damascene铜的沟槽水平。用ECP去除Cu后，用低压(LP) CMP (<1 psi)去除屏障(WN)。由于与Ta(N)相比，WN具有更高的化学敏感性，因此在LP-CMP中获得了实际的抛光速率。新开发的CVD/PVD叠置WN势垒与多孔低k的相容性好，具有良好的侵蚀性能和较低的通孔电阻。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fragile porous low-k/copper integration by using electro-chemical polishing

A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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