多项目晶圆的平面规划

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI:10.1109/VDAT.2006.258145

Meng-Chiou Wu, Shr-Cheng Tsai, Rung-Bin Lin

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引用次数: 4

摘要

对于多项目晶圆，在一个以上的平面规划芯片尚未进行调查。在本文中，我们提出了两种方法来解决这个问题。我们首先将这一问题与预先选择的网线尺寸表述为混合整数线性规划(MILP)模型。然后，我们提出了一种兼容性驱动的B*树解剖搜索(CBTDS)启发式算法。对两线平面规划芯片的实验表明，MILP模型过于复杂，无法得到很好的结果，而CBTDS模型非常有效。与原始解决方案相比，CBTDS获得的平面图使用的晶圆减少了37%

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Floorplanning Multiple Reticles for Multi-project Wafers

Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers

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2006 International Symposium on VLSI Design, Automation and Test

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