低温(400°C)沉积的SiCO low k=4.5间隔层在3D VLSI集成中的研究

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI:10.1109/IEDM.2015.7409656

D. Benoit, J. Mazurier, B. Varadarajan, S. Chhun, S. Lagrasta, C. Gaumer, D. Galpin, C. Fenouillet-Béranger, D. Vo-Thanh, D. Barge, R. Duru, R. Beneyton, B. Gong, N. Sun, N. Chauvet, P. Ruault, D. Winandy, B. van Schravendijk, P. Meijer, O. Hinsinger

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引用次数: 6

摘要

首次从3D VLSI集成的角度评估了400°C沉积的新型SiCO低k间隔材料的兴趣。SiCO低k值(4.5 vs 7 SiN)的优势在整个集成过程中得以保留，并转化为14FDSOI技术中FO3环形振荡器的有效电容和延迟降低5%。此外，在厚氧化物器件上，NMOS击穿电压提高了3.5V，漏电流降低了0.7 decade。这种电气性能加上低温沉积使SiCO成为CoolCube™集成方案中3D超大规模集成电路的非常有吸引力的候选者。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.

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2015 IEEE International Electron Devices Meeting (IEDM)

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