S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani
{"title":"采用157nm光刻技术的70nm工艺节点抗蚀图案转移新工艺","authors":"S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani","doi":"10.1109/VLSIT.2002.1015451","DOIUrl":null,"url":null,"abstract":"A novel resist pattern transfer process for the 70 nm technology node is presented using 157-nm lithography. By using newly developed 157-nm resists and a 157-nm microstepper (NA=0.60), sub-100 nm resist patterns are fabricated. Three types of structures are presented for the pattern transfer process. Two of these are hard mask (HM) processes. and the other is a bi-layer process using Si-containing resist. For all these structures, the underlayers of resist work well as anti-reflecting layers. By optimizing the RIE gas conditions, resist patterns are successfully transferred to the underlayer. Using the HM as an etching mask, sub-100 nm gate patterns are fabricated.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Novel resist pattern transfer process for 70 nm technology node using 157-nm lithography\",\"authors\":\"S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani\",\"doi\":\"10.1109/VLSIT.2002.1015451\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel resist pattern transfer process for the 70 nm technology node is presented using 157-nm lithography. By using newly developed 157-nm resists and a 157-nm microstepper (NA=0.60), sub-100 nm resist patterns are fabricated. Three types of structures are presented for the pattern transfer process. Two of these are hard mask (HM) processes. and the other is a bi-layer process using Si-containing resist. For all these structures, the underlayers of resist work well as anti-reflecting layers. By optimizing the RIE gas conditions, resist patterns are successfully transferred to the underlayer. Using the HM as an etching mask, sub-100 nm gate patterns are fabricated.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"87 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015451\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel resist pattern transfer process for 70 nm technology node using 157-nm lithography
A novel resist pattern transfer process for the 70 nm technology node is presented using 157-nm lithography. By using newly developed 157-nm resists and a 157-nm microstepper (NA=0.60), sub-100 nm resist patterns are fabricated. Three types of structures are presented for the pattern transfer process. Two of these are hard mask (HM) processes. and the other is a bi-layer process using Si-containing resist. For all these structures, the underlayers of resist work well as anti-reflecting layers. By optimizing the RIE gas conditions, resist patterns are successfully transferred to the underlayer. Using the HM as an etching mask, sub-100 nm gate patterns are fabricated.