C. Young, D. Heh, S. Nadkarni, R. Choi, J. Peterson, H. Harris, J. Sim, S. Krishnan, J. Barnett, E. Vogel, B. Lee, P. Zeitzoff, G.A. Brown, G. Bersuker
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Detection of trap generation in high-k gate stacks
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-k stacks
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