I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka
{"title":"高性能60纳米CMOS技术，增强了BST(体微束缚)结构SOI和微处理器的Cu/low-k (k=2.9)互连","authors":"I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka","doi":"10.1109/VLSIT.2002.1015436","DOIUrl":null,"url":null,"abstract":"We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors\",\"authors\":\"I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka\",\"doi\":\"10.1109/VLSIT.2002.1015436\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015436\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors
We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.
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