纳米CMOS中高速SerDes的设计与工艺失效模式综述

23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI:10.1109/VTS.2005.79

Cameron Dryden

{"title":"纳米CMOS中高速SerDes的设计与工艺失效模式综述","authors":"Cameron Dryden","doi":"10.1109/VTS.2005.79","DOIUrl":null,"url":null,"abstract":"This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Survey of design and process failure modes for high-speed SerDes in nanometer CMOS\",\"authors\":\"Cameron Dryden\",\"doi\":\"10.1109/VTS.2005.79\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.\",\"PeriodicalId\":268324,\"journal\":{\"name\":\"23rd IEEE VLSI Test Symposium (VTS'05)\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"23rd IEEE VLSI Test Symposium (VTS'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2005.79\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"23rd IEEE VLSI Test Symposium (VTS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2005.79","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

本文概述了使用CMOS工艺/spl les/130 nm制造的高速(> 1 GHz)串行接口的设计和工艺相关的电气性能失效模式。总结了各种缺陷对I/O引脚可观察性能的影响，以及ATE测试技术的含义。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Survey of design and process failure modes for high-speed SerDes in nanometer CMOS

This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

23rd IEEE VLSI Test Symposium (VTS'05)

自引率

0.00%

发文量