2RW双端口SRAM在先进技术节点中的设计挑战

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI:10.1109/IEDM.2015.7409673

K. Nii, M. Yabuuchi, Yoshisato Yokoyama, Y. Ishii, T. Okagaki, M. Morimoto, Y. Tsukamoto, Koji Tanaka, Miki Tanaka, S. Tanaka

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引用次数: 7

摘要

我们研究了先进平面/FinFET技术中两个读/写(2RW) 8T双端口(DP) SRAM的适当位单元布局。采用16纳米FinFET技术设计并制作了具有高度对称8T DP位元的256 kbit 2RW SRAM宏。wordline超速驱动的读写辅助将Vmln降低了120mv，在低于0.5 V的电压下实现了成功的操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2RW dual-port SRAM design challenges in advanced technology nodes

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

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2015 IEEE International Electron Devices Meeting (IEDM)

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