采用高品质CVD TaN栅电极的自对准超薄HfO/sub / CMOS晶体管

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015398

C. Lee, J.J. Lee, W. Bai, S. H. Bae, J. Sim, X. Lei, R. Clark, Y. Harada, M. Niwa, D. Kwong

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引用次数: 16

摘要

在本文中，我们展示并表征了具有超薄(EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub - 2/栅极介质的自对准、栅极优先的CVD TaN栅极n-和p-MOS晶体管。经过1000/spl度/C, 30 s N/sub / 2/退火后，这些晶体管没有栅极缺失的迹象，并且具有良好的热稳定性。与PVD TaN器件相比，CVD TaN/HfO/sub 2/器件具有更低的泄漏电流、更小的CV滞后、更优的界面性能、更高的跨导性以及更优的电子和空穴迁移率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode

In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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