{"title":"电源管理和测试调度中数据保留和峰值降低的供应门控方案","authors":"Tsung-Chu Huang, J.-C. Tzeng, Yuan-Wei Chao, Ji-Jan Chen, Wei-Ting Liu, Kuen-Jong Lee","doi":"10.1109/VDAT.2006.258151","DOIUrl":null,"url":null,"abstract":"Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling\",\"authors\":\"Tsung-Chu Huang, J.-C. Tzeng, Yuan-Wei Chao, Ji-Jan Chen, Wei-Ting Liu, Kuen-Jong Lee\",\"doi\":\"10.1109/VDAT.2006.258151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling
Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average
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