28nm嵌入式STT-MRAM及以后的1gbit垂直磁隧道结阵列的系统优化

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI:10.1109/IEDM.2015.7409771

Chando Park, J. Kan, C. Ching, Jaesoo Ahn, L. Xue, Rongjun Wang, A. Kontos, S. Liang, M. Bangar, Hao Chen, S. Hassan, M. Gottwald, Xiaochun Zhu, M. Pakala, Seung H. Kang

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引用次数: 39

摘要

本文演示了嵌入式STT-MRAM在28 nm逻辑节点上等效位元尺寸为22 F2的1gbit阵列垂直磁隧道结(pMTJ)的所有关键器件参数的协同优化。通过薄膜调谐和亚50 nm(直径)pMTJ的先进蚀刻，同时实现了高性能和可靠性，包括TMR = 150%， Hc > 1350 Oe, Heff 1012写入周期)。可靠切换，时间变化小(<;5 %)，减小到10 ns。此外，为了确保STT-MRAM的可靠运行，还研究了隧道屏障完整性和高温器件特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond

This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.

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2015 IEEE International Electron Devices Meeting (IEDM)

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