{"title":"具有双隧道结的25nm平面体sonos型存储器","authors":"R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita","doi":"10.1109/IEDM.2006.346945","DOIUrl":null,"url":null,"abstract":"25nm gate length bulk-planar SONOS-type memory, which has Si nanocrystalline layer between double tunnel oxides, shows excellent memory characteristics due to Coulomb blockade and quantum confinement in Si nanocrystals. A direct evidence of great advantage in trade-off between charge retention and w/e speed is shown experimentally, and it is shown that further device scaling and improvement are possible by Si nanocrystal size scaling. Double tunnel junction SONOS-type memory is a strong candidate in less than 25nm region","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction\",\"authors\":\"R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita\",\"doi\":\"10.1109/IEDM.2006.346945\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"25nm gate length bulk-planar SONOS-type memory, which has Si nanocrystalline layer between double tunnel oxides, shows excellent memory characteristics due to Coulomb blockade and quantum confinement in Si nanocrystals. A direct evidence of great advantage in trade-off between charge retention and w/e speed is shown experimentally, and it is shown that further device scaling and improvement are possible by Si nanocrystal size scaling. Double tunnel junction SONOS-type memory is a strong candidate in less than 25nm region\",\"PeriodicalId\":366359,\"journal\":{\"name\":\"2006 International Electron Devices Meeting\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2006.346945\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction
25nm gate length bulk-planar SONOS-type memory, which has Si nanocrystalline layer between double tunnel oxides, shows excellent memory characteristics due to Coulomb blockade and quantum confinement in Si nanocrystals. A direct evidence of great advantage in trade-off between charge retention and w/e speed is shown experimentally, and it is shown that further device scaling and improvement are possible by Si nanocrystal size scaling. Double tunnel junction SONOS-type memory is a strong candidate in less than 25nm region