在商业铸造厂设计抗辐射CMOS微电子元件:空间和地面辐射环境以及减轻辐射影响的设备和电路技术

R. Locoe
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引用次数: 5

摘要

只提供摘要形式。当在辐射环境中使用微电子元件时,例如元件在空间中所经历的辐射环境、核反应堆中使用的元件和用于高能物理实验的元件,必须减轻特定的退化机制,以确保元件在使用寿命期间具有适当的性能。在过去的三十年中,制造辐射硬化零件的首选方法是使用具有专门工艺的精品专用铸造厂。这种方法通常被称为过程硬化。然而,由于对抗辐射组件的需求很小,以及沿着摩尔定律推进的成本呈指数级增长,这些专用代工厂的数量急剧减少,它们仍然落后于最先进的CMOS三代以上。最近,在商用CMOS晶圆厂中开发了一种制造辐射硬化元件的新方法。在这种方法中,使用非标准晶体管拓扑,添加保护环和应用新颖的电路技术,将辐射硬度设计到组件中。本报告首先介绍了空间和地面辐射环境,然后讨论了不同辐射源对CMOS技术的影响。这包括对总电离剂量、单事件扰动、单事件闭锁和单事件瞬态辐射效应的讨论。讨论了特定的非标准晶体管拓扑结构和保护带的应用,以减轻总剂量效应。还介绍了减轻单事件影响的电路方法。这些设计方法的应用并不是没有面积和性能损失的,本文将对这些损失进行量化。还讨论了与设计硬度方法应用相关的独特可靠性问题。最后,对减轻地面辐射的影响进行了讨论。
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Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects
Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.
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