全数字占空比校正器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI:10.1109/VDAT.2006.258158

Bo-Jiun Chen, Shao-Ku Kao, Shen-Iuan Liu

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引用次数: 11

摘要

提出了一种全数字50%占空比校正器(DCC)。该DCC具有宽工作频率范围、宽输入时钟占空比范围和短锁定时间以恢复50%的占空比等特点。该数字DCC已在0.35 μ m 2P4M CMOS工艺中实现。输入时钟的可接受占空比为25% ~ 75%，频率范围为250mhz ~ 600mhz。测量到的峰值抖动在600MHz时为17.3ps。此外，该DCC通过关闭半延迟线来节省功耗。在600MHz时，其功耗为16mW

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An All-Digital Duty Cycle Corrector

An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35mum 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 17.3ps at 600MHz. Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz

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2006 International Symposium on VLSI Design, Automation and Test

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