45纳米CMOS工艺在2.4和2.2 k值下多孔CVD SiOC介电介质的工艺优化和双衰减集成

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345746

V. Arnal, R. Hoofman, M. Assous, P. Bancken, M. Brokaart, P. Brun, N. Casanova, L. Chapelon, T. Chevolleau, C. Cowache, R. Daamen, A. Farcy, M. Fayolle, H. Feldis, Y. Furukawa, C. Goldberg, L. Gosset, C. Guedj, K. Haxaire, O. Hinsinger, E. Josse, S. Jullian, O. Louveau, J. Michelon, N. Possémé, M. Rivoire, A. Roman, T. Vandeweyer, J. Verheijden, J. Torres

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引用次数: 3

摘要

采用多孔CVD SiOC低k材料进行双damascene集成，实现65 nm和45 nm工艺节点的互连。开发了介电常数为2.4和2.2的沉积工艺，并对其进行了表征。低k积分进行特征尺寸低至85 nm。研究了与超低k兼容的蚀刻和条带工艺，并成功实现了双damascene集成，物理和电气结果表明，例如低泄漏电流，通过链和线电阻。积分后的k值保持在初始值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.

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Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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