{"title":"一个内置的自检方法,用于只写内容可寻址存储器","authors":"D.K. Bhaysar","doi":"10.1109/VTS.2005.7","DOIUrl":null,"url":null,"abstract":"A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A built-in self-test method for write-only content addressable memories\",\"authors\":\"D.K. Bhaysar\",\"doi\":\"10.1109/VTS.2005.7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation.\",\"PeriodicalId\":268324,\"journal\":{\"name\":\"23rd IEEE VLSI Test Symposium (VTS'05)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"23rd IEEE VLSI Test Symposium (VTS'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2005.7\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"23rd IEEE VLSI Test Symposium (VTS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2005.7","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A built-in self-test method for write-only content addressable memories
A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation.