Closed-form simulation and robustness models for SEU-tolerant design

A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100/spl times/ improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.